An integrator employing a trapezoidal integration algorithm for use in digital differential analyzer systems. Reversible computation is achieved with respect to each integrator of the system as well as with respect to the inter-connected system of integrators by utilizing a two-interval computation cycle for each iteration of the computation. During the first interval, rectangular integration is performed wherein the Y-quantity is combined with the R-quantity in accordance with the dx- input signal thereby providing dz-overflow signals. During the second interval a trapezoidal correction quantity is algebraically added to the R-quantity, the correction quantity having a numerical value of 1/2 dx . dy. The dx- and dy- quantities utilized in computing the trapezoidal correction quantities are undelayed with respect to the iteration being performed since the dx- and dy- quantities are provided by the dz- outputs of the interconnected integrators of the system, the dz- outputs being provided during the first interval of the computation cycle.

1. A digital differential analyzer integrator having a computation cycle including first and second intervals and being responsive to a dx-signal and a dy-signal representative of dxand dy-numerical increments, respectively, comprising R-accumulator means for accumulating a numerically valued Rquantity, Y-accumulator means responsive to said dy-signal for accumulating a numerically valued Y-quantity in accordance therewith, logic means coupling said Y-accumulator means to said Raccumulator means and responsive to said dx-signal and dysignal for transmitting said Y-quantity to said R-accumulator means during said first interval in accordance with said dxincrement for combination therein with said R-quantity and for providing a correction quantity in accordance with said dx- and dy-signals to said R-accumulator means for combination therein with said R-quantity during said second interval, and overflow means coupled to said R-accumulator means for providing signals representative of the overflow thereof in response to said combination of said Y-quantity with said R-quantity.
2. An integrator of the character recited in claim 1 wherein said integrator utilizes a trapezoidal integration algorithm, and said correction quantity is a trapezoidal correction quantity representative of one-half of the algebraic product of said dx-and said dy-numerical increments.
3. An integrator of the character recited in claim 2 wherein said R-accumulator means comprises R-storage means for storing said R-quantity, and R-arithmetic means coupled with said R-storage means for algebraically adding said Y-quantity to said R-quantity when said dx-increment is positive and algebraically subtracting said Y-quantity from said R-quantity when said dx-increment is negative during said first interval and for algebraically adding said trapezoidal correction quantity to said R-quantity during said second interval.
4. An integrator of the character recited in claim 3 wherein said R-arithmetic means further includes means for maintaining said R-quantity unaltered when said dx-increment has a value of zeRo.
5. An integrator of the character recited in claim 1 wherein said Y-accumulator means comprises Y-storage means for storing said Y-quantity, and Y-arithmetic means coupled with said Y-storage means and responsive to said dy-signal for altering said Y-quantity during both said first and second intervals in accordance with said dy-increment.
6. An integrator of the character recited in claim 5 wherein said Y-arithmetic means comprises means for algebraically increasing said Y-quantity when said dy-increment is positive and algebraically decreasing said Y-quantity when said dy-increment is negative.
7. An integrator of the character recited in claim 6 wherein said means for algebraically increasing and decreasing said Y-quantity further includes means for maintaining said Y-quantity unaltered when said dy-increment has a value of zero.
8. An integrator of the character recited in claim 3 wherein said R-quantity and said Y-quantity are binary numbers, and said first and second intervals each comprise one arithmetic word time with respect to said R-quantity.
9. An integrator of the character recited in claim 8 wherein said dx-increment has a numerical magnitude equal to the numerical magnitude of the lowest order of said R-quantity and said dy-increment has a numerical magnitude equal to the numerical magnitude of the second lowest order of said R-quantity, and said R-storage means further includes a storage stage normally storing the bit of said R-quantity having a numerical significance of said lowest order of said R-quantity for combining said trapezoidal correction quantities with said R-quantity.
10. An integrator of the character recited in claim 8 wherein said logic means further includes correction storage means for storing said trapezoidal correction quantities and providing an accumulated correction quantity when two successively occurring nonzero trapezoidal correction quantities have the same sign with respect to each other and inhibiting said accumulated correction quantity when two successively occurring nonzero trapezoidal correction quantities have different signs with respect to each other.
11. An integrator of the character recited in claim 10 wherein said accumulated correction quantity has a value representative of the algebraic sum of said two successively occurring nonzero trapezoidal correction quantities, and said accumulated correction quantities provided by said correction storage means are algebraically added to said R-quantity during said second interval by said R-arithmetic means.
12. An integrator of the character recited in claim 11 with said integrator responsive to a plurality of dx-signals and a plurality of dy-signals wherein said logic means further includes means for comparing simultaneously occurring trapezoidal correction quantities and providing a summed correction quantity when two said simultaneously occurring trapezoidal correction quantities have the same sign with respect to each other and inhibiting said summed correction quantity when two said simultaneously occurring trapezoidal correction quantities have different signs with respect to each other.
13. An integrator of the character recited in claim 12 wherein said summed correction quantity has a value representative of the algebraic sum of said two simultaneously occurring trapezoidal correction quantities, and said summed correction quantities are algebraically added to said R-quantity during said second interval by said R-arithmetic means.
14. A digital differential analyzer integrator having a computation cycle including first and second intervals and responsive to dx- and dy-signals representative of dx- and dy-numerical increments comprising R-accumulator means for accumulating a numerically valued R-quantity, Y-storage means for storing a numeriCally valued Y-quantity, Y-arithmetic means coupled with said Y-storage means and responsive to said dy-signals for modifying said Y-quantity in accordance therewith, said Y-storage means and said Y-arithmetic means operatively connected to Y-accumulator means, logic means coupling said Y-accumulator means to said R-accumulator means and responsive to said dx-signal and dy-signal for transmitting said modified Y-quantity to said R-accumulator means for combination therein with said R-quantity during said first interval and for providing a correction quantity to said R-accumulator means for combination therein with the modified R-quantity during said second interval, and overflow means coupled to said R-accumulator means for providing signals representative of the overflow thereof in response to said combination of said Y-quantity with said R-quantity.
15. The integrator of claim 14 wherein during said first interval said Y-quantity is summed with said dy-increment and the sum is multiplied by said dx-increment before said modified Y-quantity is combined with said R-quantity.
16. The integrator of claim 14 wherein during said second interval said modified Y-quantity is algebraically summed with said dy-increment and stored for reinsertion during the succeeding first interval, and the corrected R-quantity is summed with one-half the product of the dy-increment and dx-increment.
17. An integrator of the character recited in claim 2 wherein said first and second intervals each comprise one arithmetic word with respect to said R-quantity.
18. An integrator of the character recited in claim 10 wherein said accumulated correction quantities provided by said correction storage means are algebraically added to said R-quantity during said second interval by said R-arithmetic means.

United States Patent [72] Inventors Joe B. Dendy;
Sam P. Liden, both of Phoenix, Ariz. [21] Appl. No. 1,654 [22] Filed Jan. 9, 1970 [45] Patented Jan. 4, 1972 1 [73] Assignee Sperry Rand Corporation [54] INTEGRATOR FOR USE IN DIGITAL DIFFERENTIAL ANALYZER SYSTEMS Palevsky, Preceedings of the I.R.E., Oct. 1953, pgs. i352- i356 (235/l52)-(DDA Pub).
Control Engineering, Sept. (235/l52)-(DDAPub).
1957, Vol. 4. Pg. 173
ABSTRACT: An integrator employing a trapezoidal integration algorithm for use in digital differential analyzer systems. Reversible computation is achieved with respect to each integrator of the system as well as with respect to the inter-con nected system of integrators by utilizing a two-interval computation cycle for each iteration of the computation. During the first interval, rectangular integration is performed wherein the Y-quantity is combined with the R-quantity in accordance with the zixinput signal thereby providing dz-overflow signals. During the second interval a trapezoidal correction quantity is algebraically added to the R-quantity, the correction quantity having a numerical value of dx dy. The dxand dyquantities utilized in computing the trapezoidal correction quantities are undelayed with respect to the iteration being performed since the dxand dyquantities are provided by the dzoutputs of the interconnected integrators of the system, the dzoutputs being provided during the first interval of the computation cycle.
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.rDnIzI Pmmmm mm u Pan NE mm WWW mwJDm QmmOPm INTEGRATOR FOR USE IN DIGITAL DIFFERENTIAL ANALYZER SYSTEMS BACKGROUND OF THE INVENTION l Field of the Invention The present invention pertains to integrators for use in digital differential analyzer computation systems. For convenience of notation, the term digital differential analyzer will hereinafter be denoted as DDA.
2. Description of the Prior Art A problem commonly encountered in DDA computation systems is that of irreversibility of computation. A computation is said to be irreversible if the dependent variable of the computation assumes two different sequences of values when the independent variable of the computation assumes, respec' tively, a sequence of values first in one direction and then in the reverse direction returning to the value from which it started. The dependent variable therefore erroneously assumes two different values for the same value of the independent variable. Such DDA systems tend to drift from the true solution of a computation as the sign of the independent variable of the computation is continuously reversed throughout the iterations performed in solving the problem. One of the known causes of irreversibility in prior art DDA systems utilizing conventional rectangular integration algorithm is the quantization of data inherent in this algorithm. As well as being irreversible, such systems tend to be inaccurate due to the roundoff error associated with the rectangular integration algorithm. In an attempt to improve the accuracy of DDA systems and to reduce the drift of the systems from the true solutions due to the irreversibility phenomenon, the trapezoidal integration algorithm has been implemented in prior art systems. The trapezoidal integration algorithm requires that a correction term equal to kdxdy be algebraically added to the integrand during each iteration of the computation. Although utilization of the trapezoidal integration algorithm has im proved the accuracy of prior art DDA systems with respect to those utilizing the rectangular integration algorithm, these systems utilizing the trapezoidal integration algorithm were still found to be irreversible. These systems were irreversible since the dxand dyinputs to each integrator of the system, from which the trapezoidal correction quantity is computed, are provided by other integrators in the interconnected system of integrators. Therefore, a dz-output of an integrator provided during a particular iteration of the computation is provided to the dxand dyinputs to other integrators of the system during the next following iteration. Therefore, since the trapezoidal correction quantity is computed from dxand dy-incrcments that may be one or more iterations delayed with respect to the iteration being performed, incorrect trapezoidal quantities may be added into the integrand causing the system to drift from the true solution.
In addition to being irreversible prior art DDA systems utilizing the trapezoidal integration algorithm tend to introduce inaccuracies into the computation since the trapezoidal correction quantities are computed from delayed data and therefore may be inaccurate.
Additionally, prior art DDA integrators utilizing the trapezoidal integration algorithm required three arithmetic units to perform the required computations. One arithmetic unit was required to increment the Y-quantity. The second arithmetic unit was required to combine the Y-quantity with the R-quantity and the third arithmetic unit was required to add the trapezoidal correction quantity to the R-quantity.
SUMMARY OF THE INVENTION The present invention provides a reversible DDA integrator that is more accurate than prior art integrators and in addition requires less equipment than the prior art configurations.
The integrator, in accordance with the present invention, utilizes an integration algorithm wherein each computation cycle or iteration is comprised of at least two intervals. During the first interval rectangular integration is performed wherein the Y-quantity is combined with the R-quantity. During the second interval a correction quantity, for example, a trapezoidal correction quantity, is combined with the R-quantity. Since the dz-outputs of the integrators of the system are primarily provided at the end of the first interval, the trapezoidal correction quantities which are computed utilizing these dz-outputs are then undelayed with respect to the iteration being performed and therefore the computations performed utilizing the integrators of the present invention are reversible.
In addition, since the correction quantities are undelayed with respect to the iterations performed, the computations of a system instrumented in accordance with the present invention tend to be more accurate than computations of systems instrumented in accordance with a prior art trapezoidal algorithm.
Additionally, whereas prior art integrators utilizing a trapezoidal algorithm required three arithmetic units as previously explained, the integrators in accordance with the present invention require only two arithmetic units. One of the arithmetic units of the present invention is utilized during the first interval to combine the Y-quantity with the R-quantity and is furthermore utilized during the second interval to combine the trapezoidal correction quantity with the R-quantity. The other arithmetic unit of the present invention is utilized during both intervals to increment or decrement the Y-quanti ty in accordance with the dy-input.
Three species of the present invention are disclosed, each utilizing a different means for adding the trapezoidal correction quantities to the R-quantity.
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 11a and lb are schematic logic diagrams, partially in block form, showing an embodiment of the invention in which the trapezoidal correction quantities are added to an additional stage of the R-storage register;
FIGS. 2a and 2b are schematic logic diagrams, partially in block form, showing another embodiment of the invention in which successive trapezoidal correction quantities are stored and combined before being added to the R-storage register;
FIGS. 3a to 3b are schematic logic diagrams, partially in block form, showing yet another embodiment of the invention having multiple inputs; and
FIG. 4 is a waveform timing diagram illustrating the waveforms of the control signals required for the circuits of FIGS. 1, 2, and 3.
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. ll, 2 and 3 illustrate three embodiments of an integrator in accordance with the present invention wherein the computation cycles therefor, each comprises two intervals. The intervals may, for example, each comprise one word time with respect to the associated R-quantities. During the first word time of a computation cycle, the Y-quantity associated with each integrator is altered in accordance with the associated dy-signal and the altered Y-quantity is combined with the associated R-quantity in accordance with the associated dxsignal. During the second word time of the computation cycle, the Y-quantity is again altered in accordance with the dysignal and the trapezoidal correction quantity is added to the R-quantity.
The illustrated integrators are implemented utilizing a ternary communication system which is characterized by the use of two conductors associated with each of the dx-, dyand dzincrements, which conductors convey the incremental information amongst the integrators of the computation system. The binary signal on one of the two wires is representative of the existence or absence of the associated dx-, dyor dz-incre ment and the binary signal on the other of the two wires is representative of the sign of the associated increment.
The integrator of the present invention generally includes a Y-storage register for storing the Y-quantity. The output of the Y-storage register is generally connected as an input to an incrementing-decrementing circuit for altering the Y-quantity in accordance with the dy-signal. The output of the incrementing-decrementing circuit is generally coupled to the input of the Y-storage register.
The output of the incrementing-decrementing circuit is also generally coupled as an input to a rectangular integration and correction quantity circuit. The rectangular integration and correction quantity circuit together with an adder-subtractor circuit combine the Y-quantity with the R-quantity during the first word time of the computation cycle and add the trapezoidal correction quantity to the R-quantity during the second word time thereof.
The integrator of the present invention also generally includes an R-storage register for storing the R-quantity. The output of the R-storage register is generally connected as an input to the adder-subtractor circuit. The adder-subtractor circuit combines the Y-quantity with the R-quantity and adds the trapezoidal correction quantity provided by the rectangular integration and correction quantity circuit to the R-quantity. The output of the adder-subtractor circuit is generally coupled to t e input of the R-storage register.
An overflow circuit, which is generally responsive to the signals provided by the adder-subtractor circuit and the rectangular integration and correction quantity circuit, provides the dz-output signals from the integrator. The numerical quantities associated with the integrator of the present invention may, for example, comprise binary numbers whose polarities may be represented in the well-known twos complement notation.
Referring now to FIG. 1, an embodiment of an integrator in accordance with the present invention is illustrated in which the trapezoidal correction quantities are added to an additional stage 31 of the R-shift register 32.
The Y-shift register 72, as previously explained, is included in the integrator for storing the Y-quantity which may comprise, for example, a binary number. A clock pulse source connected to the shift register 72 provides the shifting pulses as illustrated by waveform A of FIG. 4, for shifting the Y-binary number therethrough.
The output signal, Y of the Y-shift register 72 is connected as an input to the incrementing-decrementing circuit 73 to which the Y-quantity, Y is applied in bit serial fashion in response to the shifting pulses provided by the clock pulse source 10. The bits of the Y-quantity are shifted into the incrementing-decrementing circuit 73 in the order of increasing significance. Additionally, a dy-signal and an S,,-signal, from other integrators of the system, are applied respectively via conductors 22 and 23 as inputs to the incrementing-decrementing circuit 73. The dy-signal is applied via a NAND-gate 74 for reasons to be explained. The existence or absence of a dy-increment during a computation cycle is determined, as previously explained, by the binary state of the dy-signal present on the conductor 22 during the computation cycle. A binary ONE or a binary ZERO signal on the conductor 22 is determinant of the existence or absence thereof respectively. The S -signal is representative of the sign of the dy-increment which sign is positive or negative in accordance with the 8,,- signal being in the binary ZERO state or the binary ONE state respectively.
A second least significant bit time pulse source 18 provides the control signal, as illustrated by waveform L of FIG. 4, to the NAND-gate 74 to which the dy-input signal is also applied. The second least significant bit time pulse source 18 controls the numerical significance of the dy-increment or decrement combined with the Y-quantity by the circuit 73 in a manner to be described. The clock pulse source 10, connected generally to the incrementing-decrementing circuit 73 provides control signals thereto, as illustrated by waveform A of FIG. 4.
The incrementing-decrementing circuit 73 combines the dyincrement with the Y-quantity, Y during a computation cycle, in accordance with the dy and S,,-signals. When the S,- signal is representative of the positive sign during the computation cycle, the dy-increment is added to the Y-quantity and when the S,,-signal is representative of the negative sign during the computation cycle, the dy-increment is subtracted therefrom. When the dy-signal is representative of the absence of a dy-increment, the Y-quantity remains unaltered. The addition or subtraction of the dy-increment with respect to the Y-quantity may be performed in bit serial fashion in a conventional manner.
A Y-register initial condition pulse source 19 provides initializing signals via NAND-gate 75 to the Y-shift register 72. An initial condition control pulse source 12 provides an initial condition control signal, as illustrated by waveform B of FIG. 4 to the NAND-gate 75 and via an inverter 76 to the incrementing-decrementing circuit 73 for reasons to be explained.
The incrementing-decrementing circuit 73 provides a Y signal representative of the combined Y-quantity and dy-increment. The V rsignal is applied directly and via an inverter 70 to a flip-flop 71 which provides the Y-quantity signal, in bit serial fashion, to the input of the Y-shift register 72.
The incrementing-decrementing circuit 73 comprises, for example, a conventional serial circuit identical to the addersubtractor circuit 33 to be discussed.
The Y -signal provided by the incrementing-decrementing circuit 73 via the inverter 70 is applied as an input to the rectangular integration and trapezoidal correction circuit 50. The rectangular integration and trapezoidal correction circuit 50, together with the adder-subtractor circuit 33, as previously explained, perform rectangular integration with respect to the Y- and R-quantities during the first word time of the computation cycle and add a trapezoidal correction quantity to the R-quantity during the second word time thereof. A dxsignal and an S -signaI are applied via conductors 20 and 21 as inputs to the rectangular integration and trapezoidal correction circuit 50. The dx and the S signals are provided either from the system timing signal source, as indicated by the legend, or from other integrators of the system depending on the function performed by the integrator in the computation. The existence or absence of a dx-increment, during a computation cycle, is determined by the binary state of the dxsignal present on the conductor 20 during the computation cycle. A binary ONE or a binary ZERO signal on the conductor 20 is determinant of the existence or absence thereof respectively. The S l-signal is representative of the sign of the dx-increment which sign is positive or negative in accordance with the S signal being in the binary ZERO state or the binary ONE state respectively. A first word time pulse source 17 provides a control signal, as illustrated by waveform K of FIG. 4, to the rectangular integration and trapezoidal correction circuit 50.
During the first word time of the computation cycle, the rectangular integration and trapezoidal correction circuit 50 provides a Y' -signal, as indicated by the legend, representative of the rectangular integration function Y 'dx. The circuit50 includes a NAND-gate 56 which is responsive to the first word time pulse source 17, the Y signal and the (ix-signal and provides the Y-signal during the first word time via an inverter 58 in a manner to be explained.
The rectangular integration and trapezoidal correction circuit 50 also provides an S ,-signal, which during the first word time is representative of the S ,-signal. The S,'-signal provides a control function for the adder-subtractor circuit 33 during the first word time. When the S,'-signal is in the binary ZERO state, the adder-subtractor circuit 33 algebraically adds the Y- quantity to the R-quantity. When the S,'-signal is in the binary ONE state, the circuit 33 algebraically subtracts the Y-quantity from the R-quantity. A NAND-gate 59 responsive to the first word time pulse source 17 and the S signal, during the first word time, provides the S ,'-signal via an inverter 60, in a manner to be explained.
The dy-signal and the S,,-signal, which have been previously described, are applied respectively via the conductors 22 and 23 as inputs to the rectangular integration and trapezoidal correction circuit 50. A second word time pulse source 16 and least significant bit time pulse source provide control signals, as illustrated by waveforms H and G respectively of FIG. t, to the circuit 50. The Y'-signal provided during the second word time of the computation cycle by the rectangular integration and trapezoidal correction circuit 50 is representative of the trapezoidal correction quantity /sdxziy and is derived in a manner to be explained. The S {signal provided during the second word time by the circuit 50 is representative of the sign of the trapezoidal correction. The trapezoidal correction quantity is positive when the S,:-signal is in the binary ZERO state or is negative when the S,signal is in the binary ONE state. The S signaI is provided by the rectangular integration and trapezoidal correction circuit 50, in a manner to be explained.
Referring still to the circuit 50, a NAND-gate 55, responsive to the least significant bit time pulse source 15, the second word time pulse source 16, the dy-signal and the dx-signal, provides the Y'-signal during the second word time via an inverter 58. The Y-signal during the second word time, as previously explained, is representative of the trapezoidal correction function yz'dxdy. The numerical values of the dxand dy-increments are unity with respect to the R-quantity as will be further explained hereafter. The timing associated with the least significant bit time pulse source 15 provides the one-half factor of the trapezoidal correction function in a manner to be explained.
The S,,-signal provided during the second word time represents the sign of the trapezoidal correction quantity, as previously explained, and is provided via an inverter 60 by means of inverters 51 and 52 and NAND-gates 53, 54 and 57. The S -signal, during the second word time, is representative of the Boolean expression (S S S 'S,,). This Boolean expression is logically descriptive of the conditions wherein the 8,,- signal is in the binary ZERO state, which represents the positive sign, whenever the S -signal and the S -signal represent the same sign with respect to each other; or the S ,'-signal is in the binary ONE state, which represents the negative sign, whenever the S -signal and the S -signal represent different signs with respect to each other.
The NAND-gate S3 is responsive to the S ,-signal and the 5,,- signal and the NAND-gate 54 is responsive thereto via the inverters 52 and SI, respectively. The output signals of the NAND-gates 53 and 54 are applied to the NAND-gate 57 via a wired AND configuration. The second word time pulse source to is also connected as an input to the NAND-gate 57. The output signal of the NAND-gate 57 provides the S,-signal via the inverter 60 during the second word time of the computation cycle. The SQ-signal during the second word time is representative of the described Boolean function.
The R-shift register 32 as previously explained, is included in the integrator of the present invention for storing the R- quantity which comprises, for example, a binary number. The clock pulse source 10, connected to the shift register 32, provides the shifting pulses as illustrated by waveform A of FIG. 4, for shifting the R-binary number therethrough.
The output, R of the R-shift register 32 is connected as an input to the adder-subtractor circuit 33 to which the R-quantity, R is applied in hit serial fashion in response to the shifting pulses provided by the clock pulse source 10. The bits of the R-quantity are shifted into the adder-subtractor circuit 33 in the order of increasing significance. The rectangular integration and trapezoidal correction circuit 50 provides the Y'- signal and the S,'-signal as inputs to the addersubtractor circuit 33 as previously explained. The Y' signal comprises, for example, a binary number and is provided to the adder-subtractor circuit 33 in bit serial fashion in the order of increasing bit significance.
During the first word time of the computation cycle, the adder-subtractor circuit 33 combines the Y-signal with the R signal in conventional serial arithmetic fashion. The S,'-signal determines whether the Y'-signal is added to the R-signal or subtracted therefrom. The Y'-signal is added to the R-signal when the S signaI is ZERO and is subtracted therefrom when the S,.'-signal is ONE.
During the second word time of the computation cycle, the adder-subtractor circuit 33 combines the Y'-signal, which during the second word time represents a trapezoidal correction quantity, with the R-quantity in conventional serial arithmetic fashion. The trapezoidal correction quantity is combined with the R-quantity in accordance with the 5 signal, which during the second word time is representative of the sign of the trapezoidal correction quantity. The trapezoidal correction quantity is added to the R-quantity when the S ,-signal is ZERO and is subtracted therefrom when the S,- signal is ONE.
The adder-subtractor circuit 33 provides an R -signal representative of the combined Y-signal and R-signal. The R -sigial is applied directly and via an inverter 30 to a flipflop 311 which provides the R-quantity signal, in bit serial fashion, to the input of the R-shift register 32. The adder-subtractor circuit 33 also provides a signal, C representative of the carry produced either during the first word time or the second word time of the computation cycle. An R-register initial condition pulse source 11 provides initializing signals via NAND-gate 34 to the R-shift register 32. The initial condition control pulse source 12 provides the initial condition control signal, as illustrated by waveform B of FIG. 41, to the NAND- gate 34 and via an inverter 29 to the adder'subtractor circuit 33 for reasons to be explained.
The adder-subtractor circuit 33 may comprise, for example, a conventional binary serial arithmetic circuit of a type well known in the binary computer art. The adder-subtractor circuit 33 adds the respective signals appearing at the inputs 37 and 38 thereby providing the sum thereof in bit serial fashion at the output terminal 39 when the add/sub control input 40 is in the binary ZERO state. The adder-subtractor circuit 33 subtracts the signal appearing at the input terminal 38 from the signal appearing at the input terminal 37 thereby providing the difference therebetween in bit serial fashion at the output terminal 39 when the add/sub control input 30 is in the binary ONE state.
The C -signal provided by the adder-subtractor circuit 33 is applied as an input to an overflow circuit 90. The Y-signal and the S,'-signal are also provided as inputs to the circuit 90. Control signals are provided to the circuit by the clock pulse source 10, and a most significant bit time pulse source 14. The respective control signals are illustrated by waveforms A and D of FIG. 4.
The overflow circuit 90 provides, to other integrators of the computation system, a dz-output signal and an S output signal on conductors I00 and 101, respectively.
The dz-signal is representative of the existence or absence of an overflow resulting from combining the Yquantity with the R'quantity during the first word time or adding the trape zoidal correction quantity to the Rquantity during the second word time. The dz-signa] is logically described by the Boolean expression (Y"G +Y"C,,). The existence or absence of a dzincrement is represented by a binary ONE or a binary ZERO respectively on the dz-conductor 100.
The S -signal is representative of the sign of the dz-increment and is logically described by the Boolean expression (Y" S Y "S A positive or a negative dz-increment is represented by a binary ZERO or a binary ONE respectively on the S conductor lltlll.
When a positive Y'-quantity is added to the R-quantity and the sum is greater than the capacity of the R-register, a positive overflow occurs. This condition is detected by examining the carry flip-flop of the adder-subtractor circuit 33 during the most significant bit time. If the carry flip-flop is in the ONE state, then a dz-output pulse is generated. The Boolean expression for the dz-signal as previously stated has the following significance. An overflow occurs when the carry flip-flop is in the ONE state during the most significant bit time and the Y'- quantity is positive or an overflow occurs when the carry flipflop is in the ZERO state during the most significant bit time and the Y'-quantity is negative.
The polarity of the dz-signal is represented by the S -signaI in accordance with the previously given Boolean expression which has the following significance. The dz-signal is positive, i.e., S, equals ZERO, when the Y-quantity is positive and it is added to the R-quantity or the dz-signal is negative when the Y-quantity is negative and it is subtracted from the R-quantity. The dz-signal is negative, i.e., S equals ONE, when the Y'- quantity is negative and it is added to the R-quantity or the dzsignal is negative when the Y'-quantity is positive and it is subtracted from the R-quantity.
Referring still to the circuit 90, the Y'-signal and the C signal are applied as inputs to a NAND-gate 91 and the inverses thereof are applied as inputs to a NAND-gate 92, The outputs of the NAND-gates 91 and 92 are combined via a wired AND configuration to provide the described dz-Boolean expression. The dz-Boolean signal is applied to a set input of a flip flop 94 and the inverse thereof is applied by means of an inverter 93 to a clear input thereof. An additional set input and an additional clear input to the flip-flop 94 receive a control signal from the pulse source 14 during the most significant bit time with respect to the R-binary number. By this means the dz-signal, representative of an overflow, is stored in the flip-flop 94 during the most significant bit time of the first and second word times of the computation cycle. The Q-output of the flipflop 94 provides the dz-signal on conductor 100 during the next following word time.
In a similar manner, the S -Boolean expression is implemented by inverters 95 and 98 and NAND-gates 96 and 97 and is stored in a flip-flop 99.
In operation, the integrator, as illustrated in FIG. 1, of a DDA computation system is conditioned to perfonn a computation by setting the Y-quantity and the R-quantity to proper initial values. During the initialization of the system, the initial condition control pulse source 12 provides a signal that enables the NAND-gate 34 associated with R-register 32 and enables the NANDgate 75 associated with the Y-register 72. The signal from the pulse source 12, in addition, disables the NAND-gates 35 and 36 of the adder-subtractor circuit 33 via the inverter 29 and also disables the corresponding NAND gates of the incrementing-decrementing circuit 73 via the in verter 76. The R-initial condition signal is suitably provided by an R-register initial condition pulse source 11 through the enabled NAND-gate 34 to the R-storage register comprising the flip-flop 31 and the shift register 32. The Y-initial condition signal is suitably provided by a Y-register initial condition pulse source 19 through the enabled NAND-gate 75 to the Y- storage register comprising the flip-flop 71 and the shift register 72. After the initialization procedure is completed, the integrator is conditioned for computation by the initial condition pulse source 12 whose output signal then disables the NAND-gates 34 and 75 and enables the NAND-gates 35 and 36 of the adder-subtractor circuit 33 as well as the corresponding NAND gates of the incrementing-decrementing circuit 73.
During the first and second word times of a computation cycle, the Y-quantity stored in the Y-shift register 72 is incremented or decremented in accordance with the dyand S,,signals by means of the circuit 73. A binary ZERO on the S conductor 23 renders the circuit 73 additive and a binary ONE on the s -conductor 23 renders the circuit 73 subtractive.
The Y-binary number is serially shifted into the incrementing-decrementing circuit 73 in the order of increasing bit significance. Because of the inclusion of the flip-flop 71 as part of the Y-storage register, the order of the least significant bit position of the Y-number has a numerical significance of onehalf. The flip-flop 71 is included for reasons related to the R- quantity, which reasons will become clear hereinafter.
The order of the second least significant bit of the Y-binary number has a numerical significance of unity. The incrementing-decrementing circuit 73 adds or subtracts unity from the Y-quantity when a dy-increment exists. A second least significant bit time pulse source 18 enables the NAND-gate 74 during the second least significant bit time thereby permitting the zly-signal on the conductor 22 to pass therethrough providing a signal of unit significance for the arithmetic operation, It will be appreciated that increments other than unity may be added to the Y-quantity. By altering the bit timing of the pulse source 18 with respect to the Y-quantity, increments ofa selected integral power of two may be combined with the Y-quantity in a well-known manner.
The Yi -signal, which represents the incremented or decremented Y-quantity, is shifted back into the Y-storage register comprising the flip-flop 71 and the Y-shift register 72. The incrementation or decrementation of the Y-quantity is performed during both the first and second word times of each computation cycle. The Y -signal is provided to the rectangular integration and trapezoidal correction circuit 50 via the inverter 70 as previously explained.
During the first word time of the computation cycle, the first word time pulse source 17 provides an enabling signal to the NAND-gate 56 of the rectangular integration and trapezoidal correction circuit 50. The dx-conductor 20 also provides an enabling signal to the NAND-gate 56 when a dxin' crement exists. Therefore, during the first word time, when a (ix-increment exists, the Y -signal passes through the NAND- gate 56 to provide the Y'-signal via the inverter 58 to the adder-subtractor circuit 33.
The signal provided by the first word time pulse source 17 also enables the NAND-gate 59 during the first word time of the computation cycle. Therefore, during the first word time, the S signal on conductor 21 passes therethrough to provide the S,'-signal via the inverter 60 to the adder-subtractor circuit 33.
During the first word time, the adder-subtractor circuit 33 is rendered additive or subtractive in accordance with the S signal being in the binary ZERO state or in the binary ONE state, respectively. The R -signal from the R-shift register 32, is applied in bit serial fashion in the order of increasing bit significance to the adder-subtractor circuit 33.
The adder-subtractor circuit 33 combines the Y-signal with the R -signa] in the conventional manner of a binary serial arithmetic circuit thereby providing the R signal. The R signal is then shifted back into the R-storage register comprising the flip-flop 31 and the R-shift register 32.
During the most significant bit time of the first word time of the computation cycle the overflow circuit examines the state of the carry flip-flop of the adder-subtractor circuit 33, the state of the SQ-signal and the polarity of the Y'-signal thereby determining the existence and polarity of any overflow that may have occurred during the first word time of the computation cycle in the manner previously described and stores the overflow signal in the flip-flop 94 and the polarity thereof in the flip-flop 99 thereby providing the 112- and S,- signals on the conductors 100 and 101 respectively.
During the second word time of the computation cycle, the rectangular integration and trapezoidal correction circuit 50 provides a trapezoidal correction quantity which is combined with the R-quantity by the adder-subtractor circuit 33. During the second word time, the second word time pulse source 16 provides an enabling signal to the NAND-gate 55. The dxsignal, the dy-signal and the signal from the least significant bit time pulse source 15 also provide enabling inputs thereto. The NAND-gate 55 is enabled only when all four of the inputs thereto provide binary ONE signals. The output of the NAN D- gate 55 provides the trapezoidal correction quantity via the inverter 58. A trapezoidal correction quantity therefore is provided only during the second word time when the least significant bit time pulse source 15 provides an enabling signal and the dx-increment and the dy'increment simultaneously exist. The (ix-increment and the dy-increment each has a numerical significance of unity with respect to the R-quantity. The trapezoidal correction quantity has a numerical significance of -dx -dy, which quantity is combined with the R-quantity by the adder-subtractor circuit 33.
The R-quantity, represented by the R -signal, is provided to the adder-subtractor circuit 33 by the R-storage register which comprises the flip-flop 31 and the R-shift register 32. Because the flip-flop 31 is connected in series circuit with the R-shift register, the least significant bit of the R-quantity has a numerical significance of one-half. During the second word time of the computation cycle, the R-quantity is shifted into the adder-subtractor circuit 33 in bit serial fashion in the order of increasing bit significance at the same time as the trapezoidal correction quantity signal from the NAND-gate 55 is applied thereto. Since the trapezoidal correction quantity is provided during the least significant bit time, a numerical quantity of one-half is combined with the R-quantity when the dxand the dy-increments simultaneously exist.
During the second word time of the computation cycle, the S,'-signal, provided by the circuit 50, is representative of the sign of the trapezoidal correction quantity as previously explained. The adder-subtractor circuit 33 is rendered additive or subtractive during the second word time in accordance with the S,,'-signal being in the binary ZERO state or the binary ONE state, respectively.
The trapezoidally corrected R-quantity, represented by the R signal, is shifted back into the R-storage register as previously explained with respect to the operation of the R-storage register during the first word time.
As previously described with respect to the first word time, overflows occurring as a result of combining the trapezoidal correction quantity with the R-quantity are detected by the overflow circuit 90 thereby providing the dz and S -signals as previously described.
Referring now to FIG. 2, in which like reference numerals indicate like components with respect to FIG. I, an embodiment of an integrator in accordance with the present invention is illustrated wherein successively occurring trapezoidal correction quantities are stored and combined before being added to the R-register 32.
The Y-shift register 72, as previously explained, is included in the integrator for storing the Y-quantity which comprises, for example, a binary number. The clock pulse source 10 connected to the shift register 72 provides the shifting pulses, as illustrated by wavefonn A of FIG. 4, for shifting the Y-binary number therethrough.
The output signal, Y of the Y-shift register 72 is connected as an input to the incrementing-decrementing circuit 73 to which the Y-quantity, Y is applied in bit serial fashion in response to the shifting pulses provided by the clock pulse source 10. The bits of the Y-quantity are shifted into the incrementing-decrementing circuit 73 in the order of increasing significance. Additionally, the dy-signal and the S,,-signal, from other integrators of the system, are applied respectively via the conductors 22 and 23 as inputs to the incrementingdecrementing circuit 73. The dy-signal is applied to the circuit 73 via the NAN D-gate 74 for the reasons previously discussed. The existence or absence of a dy-increment during a computa tion cycle is determined, as previously explained, by the binary state of the dy-signal present on the conductor 22 during the computation cycle. A binary ONE or a binary ZERO signal on the conductor 22 is determinant of the existence or absence thereof respectively. The s -signal is representative of the sign of the dy-increment which sign is positive or negative in accordance with the s -signal being in the binary ZERO state or the binary ONE state respectively. The least significant bit time pulse source provides the control signal, as illustrated by waveform G of FIG. 4, to the NAND-gate 74 to which the dy-input signal is also applied. The least significant bit time pulse source 15 controls the numerical significance of the dy-incrernent or decrement combined with the Y-quantity by the circuit 73 in the manner described with respect to FIG. 1. The clock pulse source 10, connected generally to the incrementing-decrementing circuit 73 provides control signals thereto, as illustrated by waveform A of FIG. 4.
The incrementing-decrementing circuit 73 combines the dyincrement with the Y-quantity, Y during a computation cycle, in accordance with the dyand S,,-signals. When the 8,,- signal is representative of the positive sign during the computation cycle, the dy-increment is added to the Y'quantity and ill) when the dy-signal is representative of the negative sign during the computation cycle, the dy-increment is subtracted therefrom. When the dy-signal is representative of the absence of a dy-increment, the Y-quantity remains unaltered. The ad dition or subtraction of the dy-increment with respect to the Y-quantity is performed in hit serial fashion in the conventional manner previously explained with respect to FIG. I. The Y-register initial condition pulse source l9 provides initializing signals via a NAN D-gate 75 to the Y-shift register 72. The initial condition control pulse source 12 provides an initial condition control signal, as illustrated by waveform B of FIG. t to the NAND-gate 75 and via an inverter 76 to the incrementing-decrementing circuit 73 for the reasons with respect to FIG. 1.
The incrementing-decrementing circuit 73 provides the 7 signal representative of the combined Yquantity and dy-increment. The Y -signal is applied via the inverter 70, in bit serial fashion, to the input of the Y-shift register 72.
The incrementing-decrementing circuit 73 comprises, for example, a conventional serial arithmetic circuit of the type previously described with respect to FIG. 1.
The Y signal provided by the incr-ementing-decrementing circuit 73 via the inverter 70 is applied as an input to the rectangular integration and correction storage circuit 107. The rectangular integration and correction storage circuit 107, together with the addersubtractor circuit 33 perform rectangular integration with respect to the Y- and R-quantities during the first word time of the computation cycle and add a correction quantity to the R-quantity during the second word time thereof. The dx-signal and the S signal are applied via the conductors 20 and 21 as inputs to the rectangular integration and correction storage circuit 107. The dxand the S signals are provided either from the system timing signal source, as indicated by the legend, or from other integrators of the system depending on the function performed by the integrator in the computation. The existence or absence of a dxincrement, during a computation cycle, is determined by the binary state of the dx-signal present on the conductor 20 during the computation cycle. A binary ONE or a binary ZERO signal on the conductor 20 is determinant of the existence or absence thereof respectively. The S -signal is representative of the sign of the dx'increment which sign is positive or negative in accordance with the S -signal being in the binary ZERO state or binary ONE state, respectively. The first word time pulse source 17 provides the control signal, as illustrated by wavefon'n K of FIG. 4, to the rectangular integration and correction storage circuit 107.
During the first word time of the computation cycle, the rectangular integration and correction storage circuit 1107 provides the Y-signal, as indicated by the legend, representative of the rectangular integration function Y -dx. The circuit I07 includes a NAND-gate 114 which is responsive to the first word time pulse source 17, the Y signal and the a'x-signal and provides the Y-signal during the first word time via an inverter I20 in a manner to be explained.
The rectangular integration and correction storage circuit 107 also provides the S ,'-signal which, during the first word time, is representative of the S -signal. The S,'-signal provides a control function for the adder-subtractor circuit 33 during the first word time. When the S,-signal is in the binary ZERO state, the adder-subtractor circuit 33 algebraically adds the Y- quantity to the R-quantity. When the Sj-signal is in the binary ONE state, the circuit 33 algebraically subtracts the Y-quantity from the R-quantity. A NAND-gate I12 responsive to the first word time pulse source I7 and the S,-signal, provides the S '-signal during the first word time via an inverter 115 in a manner to be explained.
The dy-signal and the S,,-signal are applied respectively via the conductors 22 and 23 as inputs to the rectangular integration and correction storage circuit 107. The second word time pulse source 16 and the least significant bit time pulse source 15 provide control signals, as illustrated respectively by waveforms H and G of FIG. 41, to the circuit 107. The Y-signal provided during the second word time of the computation cycle by the rectangular integration and correction storage circuit 107 is representative of the algebraic accumulation of successively occurring pairs of trapezoidal correction quantities and is derived in a manner to be explained. The S ,-signal provided during the second word time by the circuit 107 is representative of the sign of the accumulated trapezoidal correction. The accumulated correction quantity is positive when the S,-signal is in the binary ZERO state or is negative when the S,.-signal is in the binary ONE state. The S ,'-signal is provided by the rectangular integration and correction storage circuit 107 in a manner to be explained.
Referring still to the circuit 107, a NAND-gate 113, responsive to the second word time pulse source 16, the dy-signal and the (ix-signal, provides a signal to the trigger input of a flip-flop 117 via an inverter 116. The signal provided by the inverter 116, which signal is also applied as enabling inputs to NAND- gates 118 and 119, is representative of the simultaneous existence of the dx-increment and the dy-increment during the second word time of a computation cycle. The signal provided by the inverter 116, therefore, is representative of the trapezoidal correction quantity which has a numerical significance of one-half.
The Q-output and the O-output of the flip-flop 117 are connected to a C-input and to an S-input thereof, respectively. The flip-flop 117, therefore, toggles in response to pulse signals appearing on the T-input thereof. The flip-flop 117 may be selected to be of the type responsive to the trailing edges of pulses applied to the T-input thereof. The O-output and the O-output of the flip-flop 117 are connected as enabling inputs to the NAND-gates 1 18 and 1 19 respectively. The least significant bit time pulse source also provides enabling signals to the NAND-gates 118 and 1 19. The NAND- gates 1 l8 and 119, in addition, are responsive to the S ,-signal and the ,'-signal respectively. The circuit comprising the NAND-gates 113, 118 and 119, the inverter 116 and the fiip flop 117 provides the Y'-signal, via the inverter 120, during the second word time, in a manner to be explained.
The S -signal provided during the second word time, as previously explained, represents the sign of the accumulated correction quantity and is provided via the inverter 115 by means of inverters 108 and 109 and NAND-gates 110 and 111. The S, .-signal, during the second word time, is representative of the Boolean expression (S,"S,,+,-S,,). This Boolean expression is logically descriptive of the conditions wherein the S,-signal is in the binary ZERO state, which represents the positive sign, whenever the S -Signal and the S,,-signal represent the same sign with respect to each other; or the S,- signal is in the binary ONE state, which represents the negative sign, whenever the S -signaI and the S -signal represent different signs with respect to each other.
The NAND-gate 110 is responsive to the second word time pulse source 16, the S -signal via the inverter 108 and the 8,,- signal. Similarly, the NAND-gate 111 is responsive to the second word time pulse source 16, the S,,-signal via the inverter 109 and the S -signal. The output signals of the NAND- gates 110 and 111 are applied as the input to the inverter 115 via a wired AND configuration. The output signal of the inverter 1 15 provides the S -signal during the second word time of the computation cycle. The S ,'-signal during the second word time is representative of the above given Boolean function.
The R-shift register 32, as previously explained, is included in the integrator of the present invention for storing the R quantity which comprises, for example, a binary number. The clock pulse source 10, connected to the shift register 32, provides the shifting pulses as illustrated by waveform A of FIG. 4, for shifting the R-binary number therethrough.
The output, R of the R-shift register 32 is connected as an input to the adder-subtractor circuit 33 to which the R-quantity, R is applied in bit serial fashion in response to the shifting pulses provided by the clock pulse source 10. The bits of the R-quuntity are shifted into the addcr-subtractor circuit 33 in the order of increasing significance. The rectangular integration and correction storage circuit 107 provides the Y'-signal and the S,'-signal as inputs to the adder-subtractor circuit 33, as previously explained. The Y'-signa| comprises, for example, a binary number and is provided to the adder-subtractor circuit 33 in bit serial fashion in the order of increasing bit significance.
During the first word time of the computation cycle, the adder-subtractor circuit 33 combines the Y'-signal with the R- signal in serial arithmetic fashion. The S,-signal determines whether the Y-signal is added to the R-signal or subtracted therefrom in the manner previously explained with respect to FIG. 1.
During the second word time of the computation cycle, the adder-subtractor circuit 33 combines the Y-signal, which during the second word time represents an accumulated correction quantity, with the R-quantity in serial arithmetic fashion. The correction quantity is combined with the R-quantity, in a manner to be explained, in accordance with the S,- signal, which during the second word time is representative of the sign of the correction quantity.
The adder-subtractor circuit 33 provides the R signal representative of the combined Y-signal and R-signal. The R -signal 'is applied via an inverter 30, in bit serial fashion to the input of the R-shift register 32. The adder-subtractor circuit 33 also provides the signal, C representative of the carry produced either during the first word time or the second word time of the computation cycle.
The R-register initial condition pulse source 11 provides initializing signals via a NAND-gate 34 to the R-shift register 32. The initial condition control pulse source 12 provides the initial condition control signal, as illustrated by waveform B of FIG. 4 to the NAND-gate 34 and via an inverter 29 to the adder-subtractor circuit 33 for the reasons previously explained with respect to FIG. 1.
The adder-subtractor circuit 33 comprises, for example, a conventional serial arithmetic circuit of the type previously described with respect to FIG. 1.
The C -signal, provided by the adder-subtractor circuit 33, is applied as an input to the overflow circuit 90. The Y'-signal and the S ,-signal are also provided as inputs to the circuit 90. Control signals are provided to the circuit by the clock pulse source 10 and the most significant bit time source 14. The respective control signals are illustrated by waveforms A and D of FIG. 4.
The overflow circuit 90 provides, to other integrators of the computation system, the dz-output signal and the S -output signal on the conductors and 101, respectively, as previously explained with respect to FIG. 1.
In operation, the integrator as illustrated in FIG. 2, of a DDA computation system, is conditioned to perform a computation by setting the Y-quantity and the R-quantity to proper initial values in the manner described with respect to FIG. 1. After the initialization procedure is completed, the integrator is conditioned for computation by the initial condition control source 12 as previously explained.
During the first and second word times of a computation cycle, the Y-quantity stored in the Y-shift register 72 is incre mented or decremented in accordance with the dyand S,- signals by means of the circuit 73. A binary ZERO on the 8,,- conductor 23 renders the circuit 73 additive and a binary ONE on the s -conductor 23 renders the circuit 73 subtractive in the manner previously explained with respect to FIG. 1.
The Y-binary number is serially shifted into the incrementing-decrementing circuit 73 in the order of increasing bit significance. The order of the least significant bit of the Y-binary number has a numerical significance of unity. The incrementing-decrementing circuit 73 adds or subtracts unity from the Y-quantity when a dy-increment exists. The pulse source 15 enables the NAND-gate 74 during the least significant bit time thereby permitting the dy-signal on conductor 22 to pass therethrough providing a signal of unit significance for the arithmetic operation in a manner similar to that previously described with respect to FIG. 1. The Y signal, which represents the incremented or decremented Y-quantity, is shifted back into the Y-shift register 72. The incrementation or decrementation of the Y-quantity is performed during both the first and second word times of each computation cycle. The Y signal is provided to the rectangular integration and correction storage circuit 107 via the inverter 70 as previously explained.
During the first word time of the computation cycle, the first word time pulse source 17 provides an enabling signal to the NAND-gate 114 of the rectangular integration and correction storage circuit 107. The (ix-conductor 20 also provides an enabling signal to the NAND-gate 114 when a dx-increment exists. Therefore, during the first word time when a nixincrement exists, the Y signal passes through the NAND- gate 114 to provide the Y'-signal, via the inverter 120, to the adder-subtractor circuit 33.
The signal provided by the first word time pulse source 17 also enables the NAND-gate 112 during the first word time of the computation cycle. Therefore, during the first word time, the S -signal on conductor 21 passes therethrough to provide the S signal via the inverter 115 to the adder-subtractor circuit 33.
During the first word time, the adder-subtractor circuit 33 is rendered additive or subtractive in accordance with the S signal being in the binary ZERO state or in the binary ONE state respectively. The R -signal, from the R-shift register 32 is applied in bit serial fashion, in the order of increasing bit significance, to the adder-subtractor circuit 33. The circuit 33 combines the Y'-signal with the R -signal providing the R signal via the inverter 30 in the manner previously explained with respect to FIG. 1. The R -signal is then shifted back into the R-shift register 32.
The overflow circuit 90 detects any overflows that may have occurred during the first word time and provides the dz-signal and the S -signal in the manner previously described with respect to FIG. 1.
During the second word time of the computation cycle, the rectangular integration and correction storage circuit 107 provides an accumulated correction quantity which is combined with the R-quantity by the adder-subtractor circuit 33. During the second word time, the second word time pulse source 16 provides an enabling signal to the NAND-gate 113. The ixsignal and the dy-signal also provide enabling inputs thereto. The NAND-gate 113 is enabled only when all three of the in puts thereto provide binary ONE signals. Thus, the NAND- gate 113 provides an output signal representative of the existence of a trapezoidal correction quantity during the second word time whenever the (ix-increment and the dy-increment simultaneously exist. The trapezoidal correction quantity has a numerical significance of one-half with respect to the R- quantity. The flip-flop 117 is toggled in response to successively occurring trapezoidal correction quantities as previously explained. The trapezoidal correction quantity signal also provides enabling inputs to the NAND-gates 118 and 119 via the inverter 116. The S ,'-signal provides an enabling input to the NANDgate 118 whenever the trapezoidal correction quantity is negative and the -signal provides an enabling input to the NANDgate 119 whenever the trapezoidal correction quantity is positive.
If, for example, two successive negative trapezoidal correction quantities should occur, the first occurring quantity would toggle the flip-flop 117 to the Q-state thereby enabling NAND-gate 118. This first occurring trapezoidal correction quantity is, in effect, stored in the flip-flop 117. When the second negative trapezoidal correction quantity occurs, it passes through the previously enabled gate 118, thereby providing an accumulated correction quantity signal via the inverter 120. This second trapezoidal quantity then resets flipflop 117 to the O-state. The least significant bit time pulse source 18, permits the NAND-gate 118 to be enabled only during the least significant bit time of the second word time. The accumulated correction quantity signal therefore has a numerical significance of unity with respect to the R-quantity for reasons to be discussed later.
Should, however, the second occurring trapezoidal correction quantity, of the cited example, have a positive sign, the NAND-gate 118 will be disabled by the S,-signal, thus not providing an accumulated correction quantity for the two successively occurring trapezoidal correction quantities having opposite signs with respect to each other. The accumulated correction quantity provided via the inverter 121) during the least significant bit time of the second word time is combined with the R-quantity by the adder-subtractor circuit 33.
The R-quantity, represented by the R -signal, is provided to the adder-subtractor circuit 33 by the R-shift register 32. The least significant bit of the R-quantity has a numerical significance of unity. During the second word time of the computation cycle, the R-quantity is shifted into the adder-subtractor circuit 33 in bit serial fashion in the order of increasing bit significance at the same time as the accumulated correction quantity signal from the inverter 120 is applied thereto. Since the accumulated correction quantity signal is provided during the least significant bit time of the R-quantity signal, a numerical value of unity is combined with the R-quantity when two successively occurring trapezoidal correction quantities of like sign have been accumulated by the correction storage flip-flop 117.
During the second word time of the computation cycle, the S ,'-signal provided by circuit 107, is representative of the sign of the accumulated correction quantity as previously explained. The adder-subtractor circuit 33 is rendered additive or subtractive during the second word time in accordance with the SQ-signal being in the binary ZERO state or the binary ONE state respectively in the manner previously described with respect to FIG. 1.
The corrected R-quantity, represented by the R -signal, is then shifted back into the R-shift register 32.
The overflow circuit 90, which is responsive to the C signal, the Y'signal and the S ,.-signal, provides the dz-output signal and the S -Output signal on the conductors 1110 and 101, respectively, in the manner previously explained with respect to FIG. 1.
Referring now to FIG. 3 in which like reference numerals indicate like components with respect to FIGS. 1 and 2, an embodiment of an integrator in accordance with the present invention is illustrated wherein multiple inputs are combined to provide the integrand in accordance with the equation dz=Y,dx,+Y dx- A Y -shift register 310 is included in the integrator for storing the Y -quantity which comprises, for example, a binary number. The clock pulse source 10 connected to the shift register 310 provides the shifting pulses, as illustrated by waveform A of FIG. 4, for shifting the Y,-binary number therethrough.
The output signal, Y of the Y -shift register 310 is connected as an input to an incrementing-decrementing circuit 311 to which the Y,-quantity, Y is applied in bit serial fashion in response to the shifting pulses provided by the clock pulse source 10. The bits of the Y quantity are shifted into the incrementing-decrementing circuit 311 in the order of in creasing significance. Additionally, the dy,-signal and the S, signal, from other integrators of the system, are applied respectively via the conductors 312 and 313 as inputs to the incrementing-decrementing circuit 311. The dy,-signal is applied to the circuit 311 via the NAND-gate 314 for the reasons previously discussed with respect to FIGS. 1 and 2. The existence or absence of a dy,-increment during a computation cycle is determined by the binary state of the dy -signal present on the conductor 312 during the computation cycle. A binary ONE or a binary ZERO signal on the conductor 312 is determinant of the existence or absence thereof respectively. The S,,,-signal is representative of the sign of the dy -increment which sign is positive or negative in accordance with the 8,,- signal being in the binary ZERO state or the binary ONE state respectively. The least significant bit time pulse source 15 propulse source 10, connected to the incrementing-decrementing circuit 311 provides control signals thereto, as illustrated by waveform A of FIG. 4.
The incrementing-decrementing circuit 311 combines the dy -increment with the Y -quantity, Y during a computation cycle, in accordance with the dy,- and S,,,-signals. When the S,,,-signal is representative of the positive sign during the computation cycle, the dy,-increment is added to the Y -quantity and when the dy,-signal is representative of the negative sign during the computation cycle, the dy,-increment is subtracted therefrom. When the dy -signal is representative of the absence of a dy -increment, the Y -quantity remains unaltered. The addition or subtraction of the dy -increment with respect to the Y -quantity is performed in bit serial fashion in the conventional manner previously explained with respect to FIGS. 1 and 2.
It will be appreciated that although the apparatus for providing initial condition signals to the registers of the system, which apparatus is illustrated in FIGS. 1 and 2, is not shown in FIG. 3, similar means may be included to provide this function.
The incrementing-decrementing circuit 311 provides the T -signal representative of the combined Y -quantity and dy -increment. The V -signal is applied via an inverter 315, in bit serial fashion, to the input of the Y -shift register 310.
The incrementing-decrementing circuit 311 comprises, for example, a conventional serial arithmetic circuit of the type previously described with respect to FIGS. 1 and 2.
A Y -shift register 317 is included in the integrator for storing the Y quantity which comprises, for example, a binary number. The clock pulse source connected to the shift register 317 provides the shifting pulses, as illustrated by waveform A of FIG. 4, for shifting the Y -binary number therethrough.
The output signal, Y of the Y -shift register 317 is connected as an input to an incrementing-decrementing circuit 320 to which the Y -quantity, Y is applied in bit serial fashion in response to the shifting pulses provided by the clock pulse source 10. The bits of the Y -quantity are shifted into the incrementing-decrementing circuit 320 in the order of increasing significance. Additionally, a dy -signal and an S signal, from other integrators of the system, are applied respectively via the conductors 121 and 122 as inputs to the incrementing-decrementing circuit 320. The dy -signal is applied to the circuit 320 via the NAND-gate 123 for the reasons previously discussed with respect to FIGS. 1 and 2. The existence or absence of a dy -increment during a computation cycle is determined by the binary state of the dy -signal present on the conductor 121 during the computation cycle. A binary ONE or a binary ZERO signal on the conductor 121 is determinant of the existence or absence thereof respectively. The S -signal is representative of the sign of the dy -increment which sign is positive or negative in accordance with the S -signal being in the binary ZERO state or the binary ONE state respectively.
The least significant bit time pulse source provides the control signal, as illustrated by waveform G of FIG. 4, to the NAND-gate 123 to which the dy -input signal is also applied. The least significant bit time pulse source 15 controls the numerical significance of the dy -increment or decrement combined with the Y -quantity by the circuit 320 in the manner described with respect to FIGS. 1 and 2. The clock pulse source 10, connected to the incrementing-decrementing circuit 320 provides control signals thereto, as illustrated by waveform A of FIG. 4.
The incrcmenting-decrementing circuit 320 combines the a'y -incrcment with the Y -quantity, Y during a computation cycle, in accordance with the dy and S -signals. When the S -signal is representative of the positive sign during the computation cycle, the dy -increment is added to the Y -quantity and when the dy -signal is representative of the negative sign during the computation cycle, the dy -increment is subtracted therefrom. When the dy -signal is representative of the absence of a dy -increment, the Y -quantity remains unaltered. The addition or subtraction of the dy -increment with respect to the Y -quantity is performed in bit serial fashion in the conventional manner previously described with respect to FIGS. 1 and 2.
The incrementing-decrementing circuit 320 provides the V -signal representative of the combined Y -quantity and dy -increment. The Y -signal is applied via an inverter 124, in bit serial fashion, to the input of the Y -shift register 117.
The incrementing-decrementing circuit 320 comprises, for example, a conventional serial arithmetic circuit of the type previously described with respect to FIGS. 1 and 2.
The X signal provided by the incrementing-decrementing circuit 320 via the inverter 124 as well as the Y,,.,-signal provided by the incrementing-decrementing circuit 311 via the inverter 315 are applied as inputs to a multi-input rectangular integration and trapezoidal correction circuit 316. The multiinput rectangular integration and trapezoidal correction circuit 316, together with addersubtractor circuits 318 and 319 perform combined rectangular integration with respect to the Y,-, Y and R- quantities during the first word time of the computation cycle in a manner to be described and add a correction quantity to the R-quantity during the second word time thereof.
A dx -signal and an S -signal are applied respectively via the conductors 143 and 144 as inputs to the multi-input rectangular integration and trapezoidal correction circuit 316. The dx,- and the S -signals are provided either from the system timing signal source, as indicated by the legend, or from other integrators of the system depending on the function performed by the integrator in the computation. The existence or absence of a (Ln-increment, during a computation cycle, is determined by the binary state of the dx,-signal present on the conductor 143 during the computation cycle. A binary ONE or a binary ZERO signal on the conductor 143 is determinant of the existence or absence thereof respectively. The S ,-signal is representative of the sign of the dx -increment which sign is positive or negative in accordance with the S,,-signal being in the binary ZERO state or binary ONE state, respectively.
In a similar manner, a dx -signal and an S -signal are applied respectively via the conductors 147 and I25 as inputs to the multi-input rectangular integration and trapezoidal circuit 316. The dx and S -signals are provided either from the system timing signal source or from other integrators of the system depending on the function performed by the integrator in the computation. The existence or absence of a dx -increment, during a computation cycle, is determined by the binary state of the dx -signal present on the conductor 147 during the computation cycle. A binary ONE or a binary ZERO signal on the conductor 147 is determinant of the existence or absence thereof respectively. The S -signal is representative of the sign of the dx -increment which sign is positive or negative in accordance with the S signal being in the binary ZERO state or binary ONE state, respectively.
During the first word time of the computation cycle, the multi-input rectangular integration and trapezoidal correction circuit 316 provides the Y,-signal, as indicated by the legend, representative of the rectangular integration function Y -dx The circuit 316 includes a NAND-gate 126 which is responsive to the first word time pulse source 17, the Y -signal and the dx -signal and provides the Y '-signal during the first word time via an inverter 127, in a manner to be explained. The multi-input rectangular integration and trapezoidal correction circuit 316 also provides the S,,'-signal during the first word time, which signal is representative of the S,,-signal. 'Ihc S,,- signal provides a control function for the adder-subtractor cir-

Publication number | Publication date | Assignee | Title |
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US-3204088-A | August 31, 1965 | Itt | Cumulative digital computing systems |

Title |
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Control Engineering, Sept. 1957, Vol. 4, pg. 173 (235/152)-(DDA Pub). |

Palevsky, Preceedings of the I.R.E., Oct. 1953, pgs. 1352 1356 (235/152)-(DDA Pub). |

Publication number | Publication date | Assignee | Title |
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